WIP

gb/bus.go

@@ -0,0 +1,35 @@
+package gb
+
+// import (
+// 	"fmt"
+// )
+
+// type Bus struct {
+// 	Cart *Cartridge
+// }
+
+// func NewBus(cart *Cartridge) *Bus {
+// 	bus := Bus{Cart: cart}
+
+// 	return &bus
+// }
+
+// func (bus *Bus) Read(address uint16) (byte, error) {
+// 	if address < 0x8000 {
+// 		// ROM data
+// 		return bus.Cart.Read(address), nil
+// 	} else {
+// 		return 0, fmt.Errorf("Reading from address %X not implemented!", address)
+// 	}
+// }
+
+// func (bus *Bus) Write(address uint16, value byte) error {
+// 	if address < 0x8000 {
+// 		// ROM data
+// 		bus.Cart.Write(address, value)
+
+// 		return nil
+// 	} else {
+// 		return fmt.Errorf("Writing to address %X not implemented!", address)
+// 	}
+// }

gb/console.go

@@ -11,15 +11,19 @@ const (
 )
 
 type Console struct {
+	CPU       *CPU
 	Cartridge *Cartridge
 	front     *image.RGBA
 }
 
 func NewConsole(path string) (*Console, error) {
-	cartridge := InsertCartridge(path)
+	cartridge, err := InsertCartridge(path)
+	if err != nil {
+		return &Console{}, err
+	}
 	buffer := image.NewRGBA(image.Rect(0, 0, ConsoleWidth, ConsoleHeight))
 
-	console := Console{Cartridge: cartridge, front: buffer}
+	console := Console{Cartridge: cartridge, CPU: NewCPU(), front: buffer}
 
 	return &console, nil
 }

gb/cpu.go

@@ -0,0 +1,45 @@
+package gb
+
+const CPUFrequency = 4194304
+
+type Registers struct {
+	A  byte
+	F  byte
+	B  byte
+	C  byte
+	D  byte
+	E  byte
+	H  byte
+	L  byte
+	PC uint16
+	SP uint16
+}
+
+type CPU struct {
+	Regs                Registers
+	FetchedData         uint16
+	MemoryDestination   uint16
+	DestinationIsMemory bool
+	CurrentOPcode       byte
+	// CurrentInstruction     *Instruction
+	Halted                 bool
+	Stepping               bool
+	InterruptMasterEnabled bool
+}
+
+func NewCPU() *CPU {
+	cpu := CPU{}
+	cpu.Regs = Registers{}
+	cpu.Stepping = true
+
+	return &cpu
+}
+
+func (cpu *CPU) Step() bool {
+	if cpu.Stepping {
+		cpu.Stepping = false
+		return true
+	}
+
+	return false
+}